The present invention relates to a semiconductor device and to a method of fabricating the same, and more specifically to the one which is adapted to forming a polycrystalline semiconductor layer having a highly precisely defined junction area on the side walls of a convex semiconductor layer or mesa.
The present invention relates to the structure of a semiconductor device and a method of fabricating the same, and particularly to the structure that is finely constructed and that is adapted to operating at high speeds and to a method of fabricating the same.
In the conventional semiconductor devices as disclosed in Japanese Patent Laid-Open No. 73156/1983, the base electrode of a bipolar transistor is taken out through a polycrystalline semiconductor layer sandwiched between the insulating films in order to realize high-speed operation by maintaining the parasitic capacitance small. The steps for fabricating the polycrystalline semiconductor layer that is a base electrode of the transistor, are shown in FIGS. 1A to 1E. The manufacturing steps will now be described. With reference to FIG. 1A, an n.sup.+ -type buried layer 2 is formed on a p-type silicon substrate 1, an n-type silicon epitaxial layer 3 is grown thereon, a silicon dioxide film 10 is deposited on the whole surface thereof, an insulating film other than the silicon dioxide film, such as a silicon nitride film (Si.sub.3 N.sub.4) 50 is deposited thereon, and another silicon dioxide film 20 is further deposited thereon, followed by patterning leaving three layers 10, 50 and 20 on the active region of the transistor. The silicon epitaxial layer is then etched using the three insulating layers 10, 50 and 20 as a mask, so that the active region assumes a convex shape. In this case, the silicon layer inwardly enters from the ends of the masks 10, 50, 20 due to etching.
With reference to FIG. 1B, an oxide film 30 is formed by the thermal oxidation, a silicon nitride film (Si.sub.3 N.sub.4) 60 is deposited on the whole surface, and the silicon nitride film 60 is left on the side surfaces of the convex silicon layer by selective etching.
With reference to FIG. 1C, an oxide film 40 is formed by the thermal oxidation. The silicon dioxide film grows very little on the side surfaces of the convex silicon layer but grows on the regions other than the convex or mesa area to form a thick oxide film 40.
With reference to FIG. 1D, the silicon nitride film 60 is removed and then the photoresist is applied followed by patterning (100), and a part of the silicon dioxide film 40 is then removed by etching resulting in an opening 200. In this case, the opening 200 is formed at an upper portion of the convex silicon layer.
With reference to FIG. 1E, a polycrystalline silicon layer is formed on the whole surface followed by patterning (300), so that only the side surfaces of the convex portion of the epitaxial layer will come into contact with the, polycrystalline silicon layer.
Through the above-mentioned steps, the structure can be realized in which the polycrystalline silicon layer comes into contact with the side surfaces of the convex silicon layer or mesa. However, the silicon dioxide film 40 that is formed by the thermal oxidation in FIG. 1C, also grows on the convex silicon layer in a manner as shown in FIG. 1C. When the silicon dioxide film in FIG. 1D is subjected to the etching, therefore, the area of the opening 200 on the side surface of the convex silicon layer tends to vary. Therefore, when p-type impurities are diffused from the polycrystalline silicon layer 300 in a subsequent step, it becomes highly difficult to precisely control the junction area between the p-type diffused region and the silicon epitaxial layer. Hence, the voltage V.sub.BE varies greatly across the base and the emitter in the inverse mode operation, making it difficult to adapt the device to an integrated circuit.